1. Field of the Invention
The present invention relates to semiconductor device manufacturing, and more particularly to a method for substantially reducing and eventually eliminating metal contamination that typically occurs during the fabrication of complementary metal oxide semiconductor (CMOS) transistors.
2. Background of the Invention
Metal contamination is a well-known problem in the semiconductor industry, and is particularly prevalent in forming CMOS transistors that include a polysilicon gate. In a typical CMOS transistor process flow, a gate dielectric is grown atop a surface of a semiconductor substrate and then polysilicon, i.e., polySi, is formed atop the gate dielectric. If there are any metals present on the surface during deposition of polysilicon, the polysilicon does not grow in an amorphous way. Moreover, when metals are present during polysilicon growth, the polysilicon does not grow in a flat manner atop the gate dielectric. Instead, protrusions, i.e., crystalline defects, are formed in the top surface, which hinder patterning of the polysilicon layer. Specifically, when etching the polysilicon layer containing these surface crystalline defects the etching cannot go entirely through the defects thereby creating polysilicon islands that lead to shorting of the polysilicon lines.
This shorting of the polysilicon lines to each other is particularly applicable for closed packed geometries. Such shorting is typically referred to in the art as “pcpc” shorts. This problem is clearly illustrated in FIGS. 1A and 1B where the characteristic defect is displayed. This defect is the result of polysilicon micromasking caused by metal-induced polysilicon growth. The insulator spacer foot is visible as well as the metal silicided polysilicon on the defect.
For this particular example, the metal defect “seed” is located on the surface of the gate dielectric. Traditionally, metal contamination has been removed by cleaning the wafer surface prior to formation of the gate dielectric with a heated chlorinated solution such as, for example, a Huang B cleaning solution, followed by rinsing. In addition to this process as well as other prior art cleaning processes, chlorinated high temperature oxidations can assist in removing metallics from semiconductor surfaces. One such chlorinated high temperature oxidation is a transfer gate sacrificial oxidation process that occurs following block level processing. Another such oxidation is the chlorinated gate oxidation process.
These high temperature chlorinated oxidations have been used in combination or individually through to the 0.13 μm technology for CMOS transistors. In such devices in which high temperature chlorinated oxidations are employed, the chlorinated furnace sacrificial oxidation may be replaced by an unchlorinated oxidation in a rapid thermal processor to improve cycle time and the gate oxidation process may be changed to use a non-chlorinated ambient (truly 100% N2O) to improve uniformity. The use of N2O is also required for device performance including prevention of boron penetration, reduction of tunneling leakage current, and the reduction of threshold voltage shifts caused by hot electron effects.
In addition, a nitrogen ion implant may be added to the gate dielectric to further decrease leakage current for gate dielectric thicknesses less than 20 Å. The implanted nitrogen is potentially an added source of metallics, namely iron, since the atomic mass for Fe is a multiple of nitrogen.
The combination of a non-chlorinated sacrificial oxidation, a nitrogen ion implant, and a non-chlorinated gate oxidation ambient puts a tremendous burden on the pre-gate cleaning process and subsequently decreases the process window to produce a metal free surface to the gate oxidation process.
In view of the problems associated with metal contamination, there exists a need for developing a new and improved method in which metal contamination during fabrication of the polySi-containing CMOS transistor is substantially reduced and/or eliminated.